Intel Quark SoC X1000 Core Developer's Manual page 15

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Contents-Intel Quark Core
28 Descriptor Types Used for Control Transfer .................................................................. 86
29 Use of CR3 with PAE Paging....................................................................................... 93
30 Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE) ......................................... 94
31 Format of a PAE Page-Directory Entry that Maps a 2-MByte Page.................................... 96
32 Format of a PAE Page-Directory Entry that References a Page Table................................ 97
33 Format of a PAE Page-Table Entry that Maps a 4-KByte Page ......................................... 97
34 Page Level Protection Attributes ............................................................................... 103
35 Write-Back Enhanced Intel
36 Cache Operating Modes .......................................................................................... 116
37 Write-Back Enhanced Intel
Modes .................................................................................................................. 117
38 Encoding of the Special Cycles for Write-Back Cache................................................... 119
39 Cache State Transitions for Write-Back Enhanced Intel
Core-Initiated Unlocked Read Cycles......................................................................... 124
40 Cache State Transitions for Write-Back Enhanced Intel
Core-Initiated Write Cycles...................................................................................... 125
41 Cache State Transitions During Snoop Cycles............................................................. 125
42 SMRAM State Save Map .......................................................................................... 132
43 SMM Initial Processor Core Register Settings ............................................................. 136
44 Bit Values for SMM Revision Identifier ....................................................................... 138
45 Bit Values for Auto HALT Restart .............................................................................. 139
46 I/O Instruction Restart Value ................................................................................... 140
47 Cache Flushing (Non-Overlaid SMRAM) ..................................................................... 144
48 Cache Flushing (Overlaid SMRAM) ............................................................................ 145
49 ADS# Initiated Bus Cycle Definitions ........................................................................ 152
50 Differences between CACHE# and PCD ..................................................................... 161
51 CACHE# vs. Other Intel
52 HITM# vs. Other Intel
53 INV vs. Other Intel
54 WB/WT# vs. Other Intel
55 Register Values after Reset...................................................................................... 170
56 Floating-Point Values after Reset.............................................................................. 170
57 FERR# Pin State after Reset and before FP Instructions............................................... 174
58 Pin State during Stop Grant Bus State ...................................................................... 175
59 Write-Back Enhanced Intel
Cycle.................................................................................................................... 176
60 Byte Enables and Associated Data and Operand Bytes................................................. 184
61 Generating A[31:0] from BE[3:0]# and A[31:A2]....................................................... 185
62 Next Byte Enable Values for BSx# Cycles .................................................................. 187
63 Data Pins Read with Different Bus Sizes .................................................................... 187
64 Generating A1, BHE# and BLE# for Addressing 16-Bit Devices ..................................... 189
65 Generating A0, A1 and BHE# from the Intel
66 Transfer Bus Cycles for Bytes, Words and Dwords ...................................................... 192
67 Burst Order (Both Read and Write Bursts) ................................................................. 206
68 Special Bus Cycle Encoding ..................................................................................... 221
69 Bus State Description ............................................................................................. 224
70 Snoop Cycles under AHOLD, BOFF#, or HOLD ............................................................ 228
71 Various Scenarios of a Snoop Write-Back Cycle Colliding with an On-Going Cache Fill or
Replacement Cycle ................................................................................................. 230
72 Debug Registers .................................................................................................... 247
73 LENi Encoding........................................................................................................ 248
74 RW Encoding ......................................................................................................... 248
75 Fields within Intel
76 Encoding of Operand Length (w) Field....................................................................... 255
77 Encoding of reg Field when the (w) Field is Not Present in Instruction............................ 255
October 2013
Order Number: 329679-001US
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Quark SoC X1000 Core WB/WT# Initialization.................... 115
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Quark SoC X1000 Core Write-Back Cache Operating
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Quark Core Signals ............................................................ 162
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Quark Core Signals............................................................... 163
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Quark Core Signals ................................................................... 163
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Quark Core Signals............................................................ 164
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Quark SoC X1000 Core Pin States during Stop Grant Bus
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Quark Core Instructions .............................................................. 254
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Quark SoC X1000
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Quark SoC X1000
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Quark SoC X1000 Core Byte Enables ........ 191
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Intel Quark SoC X1000 Core
Developer's Manual
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