Stpclk# Logic; Write Buffers - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
The SMI# input must be held inactive for at least four clocks after it is asserted to reset
the edge triggered logic. A subsequent SMI# might not be recognized if the SMI# input
is not held inactive for at least four clocks after being asserted.
SMI#, like NMI, is not affected by the IF bit in the EFLAGS register and is recognized on
an instruction boundary. An SMI# does not break locked bus cycles. SMI# has a higher
priority than NMI and is not masked during an NMI.
After the SMI# interrupt is recognized, the SMI# signal is masked internally until the
RSM instruction is executed and the interrupt service routine is complete. Masking the
SMI# prevents recursive SMI# calls. The SMI# input must be de-asserted for at least
four clocks to reset the edge triggered logic. If another SMI# occurs while the SMI# is
masked, the pending SMI# is recognized and executed on the next instruction
boundary after the current SMI# completes. This instruction boundary occurs before
execution of the next instruction in the interrupted application code, resulting in back-
to-back SMM handlers. Only one SMI# can be pending while SMI# is masked.
The SMI# signal is synchronized internally and should be asserted at least three CLK
periods prior to asserting the RDY# signal to guarantee recognition on a specific
instruction boundary. This is important for servicing an I/O trap with an SMI# handler.
9.3.4

STPCLK# Logic

STPCLK# is level triggered and active low. STPCLK# is an asynchronous signal, but
must remain active until the processor issues the Stop Grant bus cycle. STPCLK# may
be de-asserted at any time after the processor generates the Stop Grant bus cycle.
When the processor enters the Stop Grant state, the internal pull-up resistor of
STPCLK#, CLKMUL (for Intel
to reduce processor power consumption. The STPCLK# input must be driven high (not
floated) in order to exit the Stop Grant state. After RDY# or BRDY# is returned active
for the Stop Grant bus cycle, STPCLK# must be de-asserted for a minimum of five
clocks before being asserted again.
When the processor recognizes a STPCLK# interrupt, the processor stops execution on
the next instruction boundary (unless superseded by a higher priority interrupt) stops
the prefetch unit, empties all internal pipelines and the write buffers, generates a Stop
Grant bus cycle, and stops the internal clock. At this point, the processor is in the Stop
Grant state.
The processor cannot respond to a STPCLK# request from an HLDA state because it
cannot empty the write buffers and, therefore, cannot generate a Stop Grant cycle.
The rising edge of STPCLK# tells the processor that it can return to program execution
at the instruction following the interrupted instruction.
Unlike the normal interrupts, INTR and NMI, the STPCLK# interrupt does not initiate
acknowledge cycles or interrupt table reads. The STPCLK# order of priority among
external interrupts is shown in
9.4

Write Buffers

The Intel
performance of consecutive writes to memory. The buffers can be filled at a rate of one
write per clock until all buffers are filled.
When all four buffers are empty and the bus is idle, a write request propagates directly
to the external bus, bypassing the write buffers. If the bus is not available at the time
the write is generated internally, the write is placed in the write buffers and propagates
to the bus as soon as the bus becomes available. The write is stored in the on-chip
cache immediately if the write is a cache hit.
October 2013
Order Number: 329679-001US
Quark Core
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Quark SoC X1000 Core), and RESERVED# are disabled
Section
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Quark SoC X1000 Core contains four write buffers to enhance the
3.7.6.
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Intel Quark SoC X1000 Core
Developer's Manual
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