I/O Space; Addressing Modes; Addressing Modes Overview; Segment Register Selection Rules - Intel Quark SoC X1000 Core Developer's Manual

Architectural Overview—Intel
3.4

I/O Space

The Intel
space. The Host Bridge propagates the Intel
without any translation on to the destination bus and, therefore, provides
addressability for 64 K+3 byte locations. Note that the upper three locations can be
accessed only during I/O address wrap-around when processor bus A16# address
signal is asserted. A16# is asserted on the processor bus when an I/O access is made
to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O
access is made to 2 bytes from address 0FFFFh.
Table 3.

Segment Register Selection Rules

Code Fetch
Destination of PUSH, PUSHF, INT, CALL, PUSHA
Instructions
Source of POP, POPA, POPF, IRET, RET instructions
Destination of STOS, MOVS, REP STOS, REP MOVS
Instructions (DI is Base Register)
Other Data References, with Effective Address using
Base Register of:
[EAX]
[EBX]
[ECX]
[EDX]
[ESI]
[EDI]
[EBP]
[ESP]
The I/O ports are accessed via the IN and OUT I/O instructions, with the port address
supplied as an immediate 8-bit constant in the instruction or in the DX register. All 8-
and 16-bit port addresses are zero extended on the upper address lines. The I/O
instructions cause the M/IO# pin to be driven low.
I/O port addresses 00F8H through 00FFH are reserved for use by Intel.
I/O instruction code is cacheable.
I/O data is not cacheable.
I/O transfers (data or code) can be bursted.
3.5

Addressing Modes

3.5.1

Addressing Modes Overview

The Intel
instructions to specify operands. The addressing modes are optimized to allow the
efficient execution of high-level languages such as C and FORTRAN, and they cover the
vast majority of data references needed by high-level languages.
October 2013
Order Number: 329679-001US
®
Quark Core
®
Quark SoC X1000 Core allows 64 K+3 bytes to be addressed within the I/O
Type of Memory Reference
®
Quark SoC X1000 Core provides a total of 11 addressing modes for
®
Quark SoC X1000 Core I/O address
Implied (Default) Segment Override
Segment Use Prefixes Possible
CS
SS
SS
ES
DS
DS
DS
DS
DS
DS
SS
SS
Intel
None
None
None
None
All
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Quark SoC X1000 Core
Developer's Manual
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