Write-Back Enhanced Intel; Quark Soc X1000 Core Write-Back Cache Architecture; Write-Back Cache Coherency Protocol - Intel Quark SoC X1000 Core Developer's Manual

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On-Chip Cache—Intel Quark Core
Snoop cycles with invalidation (INV=1) cause the Write-Back Enhanced Intel
SoC X1000 Core to invalidate an individual cache line. When the snooped line is a
modified line, then the processor schedules a write-back cycle. Inquire cycles with no-
invalidation cause the Write-Back Enhanced Intel
write-back the line, when the inquired line is in M-state, and not invalidate the line.
SRESET, STPCLK#, INTR, NMI and SMI# are recognized and latched, but not serviced
during the full-cache, modified-line write-backs, caused either by the WBINVD
instruction or by FLUSH#. However, BOFF#, AHOLD and HOLD are recognized during
the full-cache, modified-line write-backs.
7.8

Write-Back Enhanced Intel

Back Cache Architecture
This section describes additional features pertaining to the write-back mode of the
Write-Back Enhanced Intel
7.8.1

Write-Back Cache Coherency Protocol

The Write-Back Enhanced Intel
cache line in one of the following four states:
• The line is valid and defined as write-back during allocation (E-state)
• The line is valid and defined as write-through during allocation (S-state)
• The line has been modified (M-state)
• The line is invalid (I-state)
These four states are the M (Modified line), E (write-back line), S (write-through line)
and I (Invalid line) states, and the protocol is referred to as the "Modified MESI
protocol." A definition of the states is given below:
M - Modified:
E - Exclusive:
S - Shared:
I - Invalid:
Every line in the Write-Back Enhanced Intel
a state that depends on both Write-Back Enhanced Intel
generated activities and activities generated by the system hardware. As the Write-
Back Enhanced Intel
subset of MESI protocol, namely MEI, is used to maintain cache coherency.
October 2013
Order Number: 329679-001US
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Quark SoC X1000 Core Write-
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Quark SoC X1000 Core.
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Quark SoC X1000 Core cache protocol supports a
An M-state line is modified (different from main memory) and
can be accessed (read/written to) without sending a cycle out
on the bus.
An E-state line is a 'write-back' line, but the line is not modified
(i.e., it is consistent with main memory). An E-state line can be
accessed (read/written to) without generating a bus cycle and a
write to an E-state line causes the line to become modified.
An S-state line is a 'write-through' line, and is consistent with
main memory. A read hit to an S-state line does not generate
bus activity, but a write hit to an S-state line generates a write-
through cycle on the bus. A write to an S-state line updates the
cache and the main memory.
This state indicates that the line is not in the cache. A read to
this line is a miss and may cause the Write-Back Enhanced
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Intel Quark SoC X1000 Core to execute a line fill (i.e., fetch the
whole line into the cache from main memory). A write to an
invalid line causes the Write-Back Enhanced Intel
X1000 Core to execute a write-through cycle on the bus.
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Quark SoC X1000 Core is targeted for uniprocessor systems, a
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Quark SoC X1000 Core only to
Quark SoC X1000 Core cache is assigned
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Quark SoC X1000 Core-
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Intel
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Quark
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Quark SoC
Quark SoC X1000 Core
Developer's Manual
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