Capture-Dr State; Shift-Dr State; Exit1-Dr State; Pause-Dr State - Intel Quark SoC X1000 Core Developer's Manual

B.3.1.4

Capture-DR State

In this state, the JTAG register captures input pin data if the current instruction is
EXTEST or SAMPLE/PRELOAD. The other test data registers, which do not have parallel
input, are not changed.
The instruction does not change in this state.
When the TAP controller is in this state and a rising edge is applied to TCK, the
controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
B.3.1.5

Shift-DR State

In this controller state, the test data register connected between TDI and TDO as a
result of the current instruction shifts data one stage toward its serial output on each
rising edge of TCK.
The instruction does not change in this state.
When the TAP controller is in this state and a rising edge is applied to TCK, the
controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if
TMS is low.
B.3.1.6

Exit1-DR State

This is a temporary state. While in this state, if TMS is held high, a rising edge applied
to TCK causes the controller to enter the Update-DR state, which terminates the
scanning process. If TMS is held low and a rising edge is applied to TCK, the controller
enters the Pause-DR state.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
B.3.1.7

Pause-DR State

The pause state allows the test controller to temporarily halt the shifting of data
through the test data register in the serial path between TDI and TDO. An example of
using this state could be to allow a tester to reload its pin memory from disk during
application of a long test sequence.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
The controller remains in this state as long as TMS is low. When TMS goes high and a
rising edge is applied to TCK, the controller moves to the Exit2-DR state.
B.3.1.8

Exit2-DR State

This is a temporary state. While in this state, if TMS is held high, a rising edge applied
to TCK causes the controller to enter the Update-DR state, which terminates the
scanning process. If TMS is held low and a rising edge is applied to TCK, the controller
enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
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Intel Quark SoC X1000 Core
Developer's Manual
306
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Intel Quark Core—Testability
October 2013
Order Number: 329679-001US