System Address Registers - Intel Quark SoC X1000 Core Developer's Manual

instructions allow the control registers to be read or loaded (at privilege level 0 only).
This restriction means that application programs or operating system procedures
(running at privilege levels 1, 2, or 3) are prevented from reading or loading the control
registers.
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Figure 14. Intel Quark SoC X1000 Core CR4 Register
Flags relevant to Intel
PSE Page Size Extension (bit 4 of CR4)
When set, enables 4MB pages with 32-bit paging.
PAE Physical Address Extension (bit 5 of CR4)
When set, enables paging to produce physical addresses with more than 32 bits.
When clear, restricts physical addresses to 32 bits. PAE must be set before entering
IA-32e mode.
SMEP SMEP-Enable Bit (bit 20 of CR4)
Enables supervisor-mode execution prevention (SMEP) when set.
Note: Features described in CR4 (VME, PVI, and PSE) in the CPUID Feature Flag should be
qualified with the CPUID instruction. The CPUID instruction and CPUID Feature Flag are
specific to particular models. (Refer to
4.4.2

System Address Registers

Four special registers are defined to reference the tables or segments supported by the
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Intel Quark SoC X1000 Core protection model. These tables or segments are: GDT
(Global Descriptor Table), IDT (Interrupt Descriptor Table), LDT (Local Descriptor
Table), TSS (Task State Segment).
The addresses of these tables and segments are stored in special registers: the System
Address and System Segment Registers, illustrated in
named GDTR, IDTR, LDTR, and TR respectively.
Architecture"
System Address Registers: GDTR and IDTR
The GDTR and IDTR hold the 32-bit linear-base address and 16-bit limit of the GDT
and IDT, respectively.
Because the GDT and IDT segments are global to all tasks in the system, the GDT
and IDT are defined by 32-bit linear addresses (subject to page translation when
paging is enabled) and 16-bit limit values.
System Segment Registers: LDTR and TR
The LDTR and TR hold the 16-bit selector for the LDT descriptor and the TSS
descriptor, respectively.
Because the LDT and TSS segments are task-specific segments, the LDT and TSS
are defined by selector values stored in the system segment registers.
Note: A programmer-invisible segment descriptor register is associated with each system
segment register.
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Intel Quark SoC X1000 Core
Developer's Manual
52
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Quark SoC X1000 Core are described below.
describes how to use these registers.
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Intel Quark Core—System Register Organization
Appendix C, "Feature Determination.")
Figure 12. These registers are
Chapter 6.0, "Protected Mode
October 2013
Order Number: 329679-001US