12Bus Cycle Restart - Intel Quark SoC X1000 Core Developer's Manual

10.3.12 Bus Cycle Restart
In a multi-master system, another bus master may require the use of the bus to enable
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the Intel
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the Intel
has completed its bus transaction.
A bus cycle may be restarted if the external system asserts the backoff (BOFF#) input.
The Intel
BOFF# is asserted, the Intel
status pins in the next clock (see
when BOFF# is asserted is aborted and any data returned to the processor is ignored.
The pins that are floated in response to BOFF# are the same as those that are floated
in response to HOLD. HLDA is not generated in response to BOFF#. BOFF# has higher
priority than RDY# or BRDY#. If either RDY# or BRDY# are asserted in the same clock
as BOFF#, BOFF# takes effect.
Figure 109. Restarted Read Cycle
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
RDY#
BRDY#
KEN#
BOFF#
BLAST#
DATA
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Intel Quark SoC X1000 Core
Developer's Manual
222
Quark SoC X1000 Core to complete its current bus request. In this situation,
Quark SoC X1000 Core must restart its bus cycle after the other bus master
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Quark SoC X1000 Core samples the BOFF# pin every clock cycle. When
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Quark SoC X1000 Core floats its address, data, and
Ti T1 T2
100
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To Processor
Figure 109 and Figure 110). Any bus cycle in progress
Tb Tb T1b T2
100
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Intel Quark Core—Bus Operation
T2 T2 T2 T2
104 108 10C
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October 2013
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