Snoop Under Hold During Replacement Write-Back; Locked Cycles - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Figure 120. Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch
CLK
HOLD
HLDA
EADS#
INV
HITM#
A31–A4
A3–A2
ADS#
BLAST#
CACHE#
RDY#
BRDY#
W/R#
10.4.3.6

Snoop under HOLD during Replacement Write-Back

Collision of snoop cycles under a HOLD during the replacement write-back cycle can
never occur, because HLDA is asserted only after the replacement write-back cycle
(burst or non-burst) is completed.
10.4.4

Locked Cycles

In both Standard and Enhanced Bus modes, the Write-Back Enhanced Intel
SoC X1000 Core architecture supports atomic memory access. A programmer can
modify the contents of a memory variable and be assured that the variable is not
accessed by another bus master between the read of the variable and the update of
that variable. This function is provided for instructions that contain a LOCK prefix, and
also for instructions that implicitly perform locked read modify write cycles. In
hardware, the LOCK function is implemented through the LOCK# pin, which indicates
October 2013
Order Number: 329679-001US
1 2 3 4 5 6
Prefetch Cycle
0 4 8
†
To Processor
7 8 9 10 11 12 13
†
Write Back Cycle
0
14 15 16 17 18 19
Prefetch
Cont.
4 8 C C
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Intel Quark SoC X1000 Core
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