Samsung S5PC100 User Manual page 1520

HDMI
3.48 ACR PACKET TRANSMISSION CONTROL REGISTER (ACR_CON, R/W, ADDRESS = 0XF030_0180)
ACR_CON
Reserved
ALT_CTS_RATE
ACR_TX_MODE
3.49 ACR PACKET TRANSMISSION CONTROL REGISTER (ACR_MCTS)
ACR_MCTS0, R, Address = 0xF030_ 0184
ACR_MCTS1, R, Address = 0xF030_ 0188
ACR_MCTS2, R, Address = 0xF030_ 018C
ACR_MCTS0
ACR_MCTS1
ACR_MCTS2
Reserved
ACR_MCTS
9.10-38
Bit
[7:5] Reserved
In some audio format, the CTS value is changed alternately.
CTS value 1 = ACR_CTS[19:0]
CTS value 2 = {ARC_CTS[19:8], ACR_LSB2}
These two values are transmitted alternately at the ratio of
this register setting.
[4:3]
00 = always CTS value 1
01 = 1:1 (CTS value 1 = CTS value2)
10 = 2:1 (CTS value 1 = CTS value2)
11 = 3:1 (CTS value 1 = CTS value2)
Measured CTS mode, this value is not used.
000 = No not Tx.
001 = Tx once – Transmit ACR packet once when packet is
available at anytime after this value is set. After transmitting,
these bits are reset to all zero.
010 = Tx ACR_TXCNT times during every VBI period
[2:0]
011 = Tx by counting video_pixel_clock for a given CTS
value in the ACR_CTS0~2 registers.
100 = Measured CTS mode. Make ACR packet with CTS
value by counting TMDS clock for
Fs x 128 / N duration. In this case, the 7 LSBs of N value
(ACR_N register) should be all zero.
Bit
[23:20] Reserved
This value is the TMDS clock cycles for N [19:7] number of
[19:0] audio sample inputs. It is valid if measured CTS mode is set
on ACR_CON register. Least significant byte first.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0
00
00
Reset Value
0
0x00001