Data Flow Through The M320 Router Packet Forwarding Engine - Juniper M Series Monitoring And Troubleshooting Manual

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Data Flow Through the M320 Router Packet Forwarding Engine

Figure 29: M160 Router Packet Forwarding Engine Components and Data

Packets arrive at an incoming PIC interface.

The PIC passes the packets to the FPC, where the Packet Director ASIC distributes

them among the I/O Manager ASICs.

The I/O Manager ASICs process the packet headers, divide the packets into 64-byte

data cells, and pass the cells through the midplane to the SFMs.

The Distributed Buffer Manager ASICs on the SFMs distribute the data cells throughout

memory buffers located on and shared by all the FPCs.

For each packet, an Internet Processor II ASIC on an SFM performs a route lookup and

decides how to forward the packet.

The Internet Processor II ASIC notifies a second Distributed Buffer Manager ASIC (on

the SFM) of the forwarding decision, and the Distributed Buffer Manager ASIC forwards

the notification to the FPC that hosts the appropriate outbound interface.

The I/O Manager ASIC on the FPC reassembles data cells in shared memory into data

packets as they are ready for transmission and passes them through the Packet

Director ASIC to the outbound PIC.

The outbound PIC transmits the data packets.

M160 Internet Router Overview on page 21

Data flows through the M320 router Packet Forwarding Engine in the sequence shown

Figure 30 on page

Chapter 4: Monitoring Key Router Components