Figure 3: Data Flow Through The Router - Juniper Core Router T Series Hardware Manual

T320 Core Router Hardware Guide

Figure 3: Data Flow Through the Router

8
Packets arrive at an incoming PIC interface.
1.
The PIC passes the packets to the FPC, where the Layer 2/Layer 3 Packet Processing
2.
ASIC performs Layer 2 and Layer 3 parsing and divides the packets into 64-byte cells.
The Switch Interface ASIC extracts the route lookup key, places it in a notification,
3.
and passes the notification to the T Series Internet Processor. The Switch Interface
ASIC also passes the data cells to the Queuing and Memory Interface ASICs for
buffering.
The Queuing and Memory Interface ASICs pass the data cells to memory for buffering.
4.
The T Series Internet Processor performs the route lookup and forwards the notification
5.
to the Queuing and Memory Interface ASIC.
The Queuing and Memory Interface ASIC sends the notification to the Switch Interface
6.
ASIC facing the switch fabric, unless the destination is on the same Packet Forwarding
Engine. In this case, the notification is sent back to the Switch Interface ASIC facing
the outgoing ports, and the packets are sent to the outgoing port without passing
through the switch fabric (see Step 13).
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