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Memory Management
Table 3-3. Memory Operations that Impose a Fence
operation
load
store
load or store
Any swap (SWP or SWPB), to a page that would create a fence, is also a fence.
3.2.6
Exceptions
The MMU can generate prefetch aborts for instruction accesses and data aborts for data memory
accesses. The types and priorities of these exceptions are described in
Architecture" on page
Data address alignment checking is enabled by setting bit 1 of the Control Register (CP15,
register 1). Alignment faults are still reported even if the MMU is disabled. All other MMU
exceptions are disabled when the MMU is disabled.
3.3
Interaction of the MMU, Instruction Cache, and Data
Cache
The MMU, instruction cache, and data/mini-data cache may be enabled/disabled independently.
The instruction cache can be enabled with the MMU enabled or disabled. However, the data cache
can only be enabled when the MMU is enabled. Therefore only three of the four combinations of
the MMU and data/mini-data cache enables are valid. The invalid combination will cause
undefined results.
Table 3-4. Valid MMU & Data/mini-data Cache Combinations
3.4
Control
3.4.1
Invalidate (Flush) Operation
The entire instruction and data TLBs can be invalidated at the same time with one command or
they can be invalidated separately. An individual entry in the data or instruction TLB can also be
invalidated. See
the Intel® XScale™ core.
3-4
X
-
1
0
2-11.
MMU
Off
On
On
Table 7-13, "TLB Functions" on page 7-11
C
0
0
0
Section 2.3.4, "Event
Data/mini-data Cache
for a listing of commands supported by
Intel® XScale™ Microarchitecture User's Manual
B
-
1
0
Off
Off
On
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