Design Considerations - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
82596 Bus Usage
Without Throttle Timers
82596 Bus Usage
With Throttle Timers
If the timers are configured to be triggered internally, the coprocessor monitors the length of time
that the HLDA input is held asserted. When this time exceeds the time programmed in the TON
timer, the coprocessor relinquishes the bus by de-asserting HOLD; and starts the TOFF timer.
If the timers are configured externally, assertion of the BREQ; input causes the coprocessor to
start the TON timer. Upon timeout, the coprocessor relinquishes the bus and starts the TOFF tim-
er. This latter configuration is particularly useful in the Intel486 processor environment, where
the processor's BREQ output can be tied directly to the coprocessor's BREQ input.
7.6.1.7

Design Considerations

The glue logic for interfacing the 82596 coprocessor to the Intel486 processor can be contained
in a single Intel 85C220 PLD, as shown in
•
Generate channel attention (CA) input to the coprocessor.
•
Generate reset (RESET) input to the coprocessor.
•
Generate processor port access (PORT#) input to the coprocessor.
•
Drive the M/IO# and D/C# processor bus signals when the coprocessor is bus master.
The coprocessor's RESET input is referred to in
to distinguish it from the processor's RESET.
To assert the CA or 596RESET signals, the processor drives a memory-mapped I/O cycle. During
such a cycle, address decode is done while monitoring CLK, ADS#, HLDA, and D0 to distin-
guish CA from 596RESET. A similar memory-mapped cycle is used to de-assert the signal. The
HLDA input to the 85C220 PLD gates the logic, so that CA or 596RESET is generated only when
HLDA is de-asserted (i.e., when the coprocessor is not bus master).
The PORT# input to the coprocessor can be generated by combinatorial logic which has an ad-
dress decode qualified by ADS# and CLK. This asserts the PORT# output for one clock. While
PORT# is asserted, the coprocessor treats the data bus as containing slave control information.
System software must ensure that the coprocessor is idle while the processor executes a port ac-
cess. This guarantees that the coprocessor does not attempt to acquire the bus by asserting HOLD.
Failure to comply with this restriction may result in the coprocessor entering an undefined state.
7-48
t1
t2
TON TOFF
Figure 7-25. Bus Throttle Timers
Figure 7-26. This logic provides four functions:
Figure 7-26
t1 = t2 + t3
t3
TON
and the text below as "596RESET"