Intel Embedded Intel486 Hardware Reference Manual page 325

31
Breakpoint 0 Linear Address
Breakpoint 1 Linear Address
Breakpoint 2 Linear Address
Breakpoint 3 Linear Address
Intel Reserved. Do not define.
Intel Reserved. Do not define.
0
LEN R W LEN R W
3 3 3 2 2 2
31
Note: 0 indicates Intel reserved: Do not define.
LENi Breakpoint Usage of Least Significant Bits in
Encoding Field Width
00 1 Byte All 32 bits used to specify a single-
byte breakpoint field.
01 2 Byte A31–A1 used to specify a two-byte
word-aligned breakpoint field. A0 in
breakpoint address register is not
used.
10 Undefined
–Do not
use this
encoding.
11 4 Byte A31–A2 used to specify a four-byte
dword-aligned breakpoint field. A0
and A1 in breakpoint address
register are not used.
PHYSICAL DESIGN AND SYSTEM DEBUGGING
16 15
B
T
LEN R W R W
LEN0 0
1 1 1 0 0
16 15
Breakpoint Address
Register i, (i = 0–3)
Figure 10-31. Debug Registers
B B
0 0 0 0 0 0 0
S D
G G L G L
0 0 0 0
D E E 3 3
DR2 = 00000005H; LEN2 = 00B
31
BKPT FLD2
DR2 = 00000005H; LEN2 = 01B
31
DR2 = 00000005H; LEN2 = 11B
31
BKPT FLD2
0
DR0
DR1
DR2
DR3
DR4
DR5
B B B B
0 0 DR6
3 2 1 0
G L G L G L
DR7
2 2 1 1 0 0
0
0
00000008H
00000004H
00000000H
0
00000008H
00000004H
BKPT FLD2
00000000H
0
00000008H
00000004H
00000000H
10-41