Intel Embedded Intel486 Hardware Reference Manual page 77

Figure 4-8 shows a single processor and a DMA device. Here, arbitration is required to determine
whether the processor, which acts as a master most of the time, or a DMA controller has control
of the bus. When the DMA wants control of the bus, it asserts the HOLD request to the processor.
The processor then responds with a HLDA output when it is ready to relinquish bus control to the
DMA device. Once the DMA device completes its bus activity cycles, it negates the HOLD signal
to relinquish the bus and return control to the processor.
Intel486™
Processor
I/O
Figure 4-8. Single Intel486™ Processor with DMA
BUS OPERATION
DMA
Address Bus
Data Bus
Control Bus
MEM
4-13