Intel Embedded Intel486 Hardware Reference Manual page 112

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
To process a floating-point error in the DOS environment, the following sequence must take
place:
1. The error is detected by the IntelDX2 and IntelDX4 processor that activates the FERR#
pin.
2. FERR# is latched so that it can be cleared by the OUT F0 instruction.
3. The latched FERR# signal activates an interrupt at the interrupt controller. This interrupt
is usually handled on IRQ13.
4. The Interrupt Service Routine (ISR) handles the error and then clears the interrupt by
executing an OUT instruction to port F0. The address F0 is decoded externally to clear the
FERR# latch. The IGNNE# signal is also activated by the decoder output.
5. Usually the ISR then executes an FNINIT instruction or other control instruction before
restarting the program. FNINIT clears the FERR# output.
Figure 4-36 illustrates a sample circuit that performs the function described above. Note that this
circuit has not been tested and is included as an example of required error handling logic.
Note that the IGNNE# input allows non-control instructions to be executed prior to the time the
FERR# signal is reset by the IntelDX2 and IntelDX4 processors. This function is implemented
to allow exact compatibility with the AT implementation. Most programs re-initialize the Float-
ing-Point Unit (FPU) before continuing after an error is detected. The FPU can be re-initialized
using one of the following four instructions: FCLEX, FINIT, FSAVE and FSTENV.
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