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E
8-9
EBC host bus interface,
9-14
EDO DRAM,
EISA
8-8
bus buffers (EBB),
8-6
bus controller,
bus interface to the EBC,
8-2
overview,
Electromagnetic interference,
Electrostatic interference,
2-12
Embedded controllers,
Embedded personal computers,
Enhanced bus mode features,
Expanded address, defined,
External cache
see Second-level cache
F
1-5
FaxBack service,
Features
10-39
debugging,
2-3
enhanced bus mode,
2-2
Intel486 processor,
2-3
SL technology,
4-33
Floating-point cycles,
Floating-point error handling,
Floating-point unit
2-6
3-15
overview,
,
performance considerations,
4-69
Flush cycles,
6-5
Fully associative cache,
3-1
Functional units,
3-7
3-8
bus interface,
to
3-10
cache,
3-14
control,
3-14
datapath,
3-15
floating-point,
3-14
instruction decode,
3-13
instruction prefetch,
3-14
integer (datapath),
memory management,
3-16
paging,
3-15
segmentation,
8-11
to
8-11
8-13
to
10-25
10-28
2-12
2-3
4-50
,
1-4
2-3
to
4-46
9-16
3-5
G
General-purpose registers,
10-2
10-3
Ground planes,
to
10-3
double layer boards,
H
4-41
HALT cycle,
Hardware transparency, with cache,
10-34
10-36
Heatsink,
to
I
7-27
I/O cycles,
I/O devices
7-5
address decoding,
7-27
non-cacheable,
I/O interface
7-10
7-12
16-bit,
to
7-14
7-16
32-bit,
to
7-7
7-9
8-bit,
to
I/O mapping vs. memory-mapping,
4-1
I/O memory space,
3-9
I/O transfers,
10-3
Impedance,
10-18
10-23
matching,
,
10-12
mismatch,
3-14
Instruction decode unit,
Instruction execution performance,
3-6
Instruction pipelining,
Instruction prefetch unit,
Instructions, notational conventions,
3-14
Integer (datapath) unit,
Intel386 processor
5-5
bus cycle mix,
differences with Intel486
7-33
7-34
processor,
to
INDEX
3-14
10-5
to
6-14
7-2
9-2
3-13
1-3
Index-3
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