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In
Figure
7-11, address lines A15–A8 are ignored to maintain simplicity. Lines A7–A2 are de-
coded to generate addresses XXE0–XXFC. When a valid cycle begins, ADS# is latched in the
flip-flop.
(6)
G1
Enable
(4)
G2A#
Inputs
(5)
G2B#
A
Select
Inputs
Inputs
Enable
†
G1
G2#
X
1
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
†
G2# = G2A# + G2B#
1 = High
0= Low Level
X = Don't Care
Figure 7-12. Internal Logic and Truth Table of 74S138
(1)
(2)
B
(3)
C
Function Table
Select
C
B
A
Y0
X
X
X
1
X
X
X
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
PERIPHERAL SUBSYSTEM
Outputs
Y1
Y2
Y3
Y4
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
(15)
Y0
(14)
Y1
(13)
Y2
(12)
Y3
Data
Outputs
(11)
Y4
(10)
Y5
(9)
Y6
(7)
Y7
Y5
Y6
Y7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
7-25
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