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SYSTEM BUS DESIGN
The integrated system peripheral (ISP), shown in
Figure
8-3, is a multi-function support periph-
eral device that integrates many system functions that are normally distributed in several VLSI
and LSI components. The ISP supports high-performance DMA operations with a programmable
seven-channel controller. It has an arbiter that provides efficient bus sharing among multiple
EISA masters and DMA devices. A programmable interrupt controller provides 15 levels of in-
terrupts which can be edge-triggered or level-sensitive on a channel-by-channel basis. Non-
maskable interrupts (NMI) are also supported. The ISP has five counters/timers that can provide
system timer interrupts for a time of day, a diskette timeout, DRAM refresh requests and other
system timing operations. The DMA controller is integrated in the ISP, and it has the necessary
logic to set up, initiate, and complete DMA transfers. Various types of DMA transfers are pro-
vided for, including single transfer, block transfer, demand transfer, and cascade modes. Buffer
chaining is also supported. The DMA controller provides the necessary timing signals to support
a 33 Mbytes/sec transfer rate. Also supported are full 32-bit addressability on all functions and
control signal support for data transfer between devices of different data widths. Each channel
can operate independently in several modes.
8-7
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