Inserting Wait States; Multiple And Burst Cycle Bus Transfers - Intel Embedded Intel486 Hardware Reference Manual

fer is complete after a single cycle. The Intel486 processor asserts BLAST# in the last cycle,
"T2", of a bus transfer.
The timing of the parity check output (PCHK#) is shown in
drives the PCHK# output one clock after RDY# or BRDY# terminates a read cycle. PCHK# in-
dicates the parity status for the data sampled at the end of the previous clock. The PCHK# signal
can be used by the external system. The Intel486 processor does nothing in response to the
PCHK# output.
4.3.1.2

Inserting Wait States

The external system can insert wait states into the basic 2-2 cycle by deasserting RDY# at the end
of the second clock. RDY# must be deasserted to insert a wait state.
ple non-burst, non-cacheable signal with one wait state added. Any number of wait states can be
added to an Intel486 processor bus cycle by maintaining RDY# deasserted.
Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
DATA
†
To Processor
‡
From Processor
The burst ready input (BRDY#) must be deasserted on all clock edges where RDY# is deasserted
for proper operation of these simple non-burst cycles.
4.3.2

Multiple and Burst Cycle Bus Transfers

Multiple cycle bus transfers can be caused by internal requests from the Intel486 processor or by
the external memory system. An internal request for a 128-bit pre-fetch requires more than one
cycle. Internal requests for unaligned data may also require multiple bus cycles. A cache line fill
requires multiple cycles to complete.
T1 T2 T2
Read
Figure 4-11. Basic 3-3 Bus Cycle
Figure 4-10. The Intel486 processor
Figure 4-11
T1 T2
†
Write
BUS OPERATION
illustrates a sim-
T2 Ti
‡
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