Smbus Design Considerations; Intel ® Ich3-S Smbus / Smlink Interface - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
I/O Controller Hub 3 (Intel
®
Figure 111. Intel ICH3-S SMBus / SMLink Interface
Host Controller and
Slave Interface
Intel
Note: Intel does not support external access of the ICH3-S's Integrated LAN controller via the SMLink
interface. In addition, Intel does not support access of the ICH3-S's SMBus Slave Interface by the
ICH3-S's SMBus host controller. Refer to the Intel
Datasheet for full functionality descriptions of the SMLink and SMBus interface.
9.5.1

SMBus Design Considerations

There is not a single SMBus design solution that may work for all platforms. One must consider the
total bus capacitance and device capabilities when designing SMBus segments. Routing the
SMBus to the PCI slots makes the design process even more challenging since they add so much
capacitance to the bus. This extra capacitance has a large affect on the bus time constant which in
turn affects the bus rise and fall times.
Regardless of the architecture used, there are some general design considerations.
•
Device class (High/Low power). Most designs use primarily High Power Devices.
•
Amount of VCC_SUSPEND current available (i.e., minimizing load of VCC_SUSPEND).
•
The pull-up resistor size for the SMBus data and clock signals is dependent on the bus load
(this includes all device leakage currents). Generally the SMBus device that may sink the least
amount of current is the limiting agent on how small the resistor may be. The pull-up resistor
may not be made so large that the bus time constant (Resistance X Capacitance) does not meet
the SMBus rise and time specification.
•
The maximum bus capacitance that a physical segment may reach is 400 pF.
•
The ICH3-S does not run SMBus cycles while in S5.
•
SMBus devices that may operate in S5 must be powered by the VCC_SUSPEND supply.
•
When the SMBus is connected to PCI, it must be connected to all PCI slots.
•
It is recommended that I
transaction in which the device is sending information to the ICH3-S, the device may not
release the SMBus when the ICH3-S receives an asynchronous reset. The BIOS uses 1.8 V to
reset the devices. SMBus 2.0-compliant devices have a timeout capability which makes them
insusceptible to this I
160
®
E7501 Chipset Platform
®
ICH3-S)
SMBus
®
ICH3-S
SMLink
Wire OR
(optional)
2
C devices be powered by the 1.8 V supply. During an SMBus
2
C issue, allowing flexibility in choosing a voltage supply.
SPD Data
Temperature on
Thermal Sensor
SMBCLK
SMBDATA
SMLink0
SMLink1
Motherboard
LAN
Controller
®
82801CA I/O Controller Hub 3 (ICH3-S)
Network
Interface Card
on PCI
Microcontroller
Design Guide