Data Transfer Mechanism; Memory And I/O Spaces - Intel Embedded Intel486 Hardware Reference Manual

All Intel486™ processors operate in Standard Bus (write-through) mode. However, when the in-
ternal cache of the Write-Back Enhanced IntelDX4™ processor is configured in write-back
mode, the processor bus operates in the Enhanced Bus mode, which is described in
When the internal cache of the Write-Back Enhanced IntelDX4 processor is configured in write-
through mode, the processor bus operates in Standard Bus mode, identical to the other embedded
Intel486 processors.
4.1

DATA TRANSFER MECHANISM

All data transfers occur as a result of one or more bus cycles. Logical data operands of byte, word
and doubleword lengths may be transferred without restrictions on physical address alignment.
Data may be accessed at any byte boundary but two or three cycles may be required for unaligned
data transfers. (See Section 4.1.2, "Dynamic Data Bus Sizing,"
Alignment.")
The Intel486 processor address signals are split into two components. High-order address bits are
provided by the address lines, A31–A2. The byte enables, BE3#–BE0#, form the low-order ad-
dress and provide linear selects for the four bytes of the 32-bit address bus.
The byte enable outputs are asserted when their associated data bus bytes are involved with the
present bus cycle, as listed in
separating two or three asserted byte enables never occur (see
byte enable patterns are possible.
Table 4-1. Byte Enables and Associated Data and Operand Bytes
Byte Enable Signal
BE0#
BE1#
BE2#
BE3#
Address bits A0 and A1 of the physical operand's base address can be created when necessary.
Use of the byte enables to create A0 and A1 is shown in
decoded to generate BLE# (byte low enable) and BHE# (byte high enable). These signals are
needed to address 16-bit memory systems. (See
Bit Memories.")
4.1.1

Memory and I/O Spaces

Bus cycles may access physical memory space or I/O space. Peripheral devices in the system can
be either memory-mapped, I/O-mapped, or both. Physical memory addresses range from
Table 4-1. Byte enable patterns that have a deasserted byte enable
Associated Data Bus Signals
D7–D0
D15–D8
D23–D16
D31–D24
Section 4.1.3, "Interfacing with 8-, 16-, and 32-
CHAPTER 4
BUS OPERATION
and Section 4.1.5, "Operand
Table 4-5 on page
(byte 0–least significant)
(byte 1)
(byte 2)
(byte 3–most significant)
Table 4-2. The byte enables can also be
Section 4.4.
4-7). All other
4-1