Intel Embedded Intel486 Hardware Reference Manual page 49

INTERNAL ARCHITECTURE
icy. The on-chip cache includes features to provide flexibility in external memory system design.
Individual pages can be designated as cacheable or non-cacheable by software or hardware. The
cache can also be enabled and disabled by software or hardware.
Internal cache memory allows frequently used data and code to be stored on-chip, reducing ac-
cesses to the external bus. RISC design techniques reduce instruction cycle times. A burst bus
feature enables fast cache fills.
When internal requests for data or instructions can be satisfied from the cache, time-consuming
cycles on the external processor bus are avoided. The bus interface unit is only involved when an
operation needs access to the processor bus. Many internal operations are therefore transparent
to the external system.
The instruction decode unit translates instructions into low-level control signals and microcode
entry points. The control unit executes microcode and controls the integer, floating-point, and
segmentation units. Computation results are placed in internal registers within the integer or
floating-point units, or in the cache. Internal storage locations (datapaths) are kept in the integer
unit.
The cache shares two 32-bit data buses with the segmentation, integer, and floating-point units.
These two buses can be used together as a 64-bit inter-unit transfer bus. When 64-bit segment
descriptors are passed from the cache to the segmentation unit, 32 bits are passed directly over
one data bus and the other 32 bits are passed through the integer unit, so that all 64 bits reach the
segmentation unit simultaneously.
The memory management unit (MMU) consists of a segmentation unit and a paging unit which
perform address generation. The segmentation unit translates logical addresses and passes them
to the paging and cache units on a 32-bit linear address bus. Segmentation allows management
of the logical address space by providing easy relocation of data and code and efficient sharing
of global resources.
The paging mechanism operates beneath segmentation and is transparent to the segmentation
process. The paging unit translates linear addresses into physical addresses, which are passed to
the cache on a 20-bit bus. Paging is optional and can be disabled by system software. To imple-
ment a virtual memory system, the Intel486 processor supports full restartability for all page and
segment faults.
The Intel486 processor instruction set includes the complete Intel386™ processor instruction set
along with extensions to serve new applications and increase performance. The on-chip memory
MMU is completely compatible with the Intel386 processor MMU. Software written for previous
members of the Intel architecture family runs on the Intel486 processor without modification.
Memory is organized into one or more variable length segments, each up to four Gbytes
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(2 bytes). A segment can have attributes associated with it that include its location, size, type
(i.e., stack, code, or data), and protection characteristics. Each task on an Intel486 processor can
have a maximum of 16,381 segments and each are up to four Gbytes in size. Thus, each task has
a maximum of 64 terabytes (trillion bytes) of virtual memory.
The segmentation unit provides four levels of protection for isolating and protecting applications
and the operating system from each other. The hardware-enforced protection allows the design
of systems with a high degree of software integrity.
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