Ebc And Isa Bus Interface Signals - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Write or read cycle (W/R#) is a bidirectional signal that is an input during EISA bus master cy-
cles. It is an output of the EBC during host bus master to EISA/ISA slave cycles, and during ISA
master cycles.
Start cycle (START#) is a bidirectional input signal to the EBC which starts cycles on the host
bus. It is an output from the EBC on host master cycles when no responses are received from the
host slaves. It is an output during ISP requests for DMA and refresh cycles. It is also an output
during ISA master I/O cycles to 8-bit devices and when the EBC translates a 32-bit or 16-bit
EISA bus master into cycles for an EISA/ISA slave with a smaller data bus size.
Command (CMD#) is an output which provides timing control within cycles. It is asserted simul-
taneously with the negation of START# and remains asserted until the cycle terminates. It is gen-
erated by the EBC during any EISA cycle.
Master burst (MSBURST#) is a bidirectional, open-collector output asserted by an EISA master
to indicate that it is capable of supporting a burst operation in the next cycle. It is an input during
EISA bus master cycles and an output during DMA cycles, when a burst mode DMA has been
selected, and when memory is capable of supporting burst operations.
Slave burst (SLBURST#) is a bidirectional open-collector signal that is asserted by EISA slaves
to indicate that they can accept burst cycles. It is an input when the ISP requests burst cycles and
an output from the EBC when an EISA master is in control. It is asserted if the host memory is
accessed and has asserted HSLBURST#.
EISA 32-bit device (EX32#) is a bidirectional, open-collector signal that is asserted by 32-bit
EISA slaves to indicate 32-bit bus size. The signal is used to determine matched or unmatched
data sizes on masters and slaves. Once the sizes are determined, the EBC assembles and disas-
sembles data and performs multiple EISA or ISA cycles when necessary.
EISA 16-bit device (EX16#) is a bidirectional, open-collector signal that is asserted by 16-bit
EISA slaves to indicate 16-bit bus size. The signal is used to determine matched or unmatched
data sizes on masters and slaves. Once the sizes are determined, the EBC assembles and disas-
sembles data and performs multiple EISA or ISA cycles when necessary.
EISA ready (EXRDY) is a bidirectional, open-collector signal which indicates that a slave is
ready to terminate a cycle. It is an input to the EBC on host master cycles which access EISA or
ISA slaves and is propagated to the host as the HRDY# signal. It is also an input for performing
DMA or refresh cycles and is propagated as DRDY. It is an output from the EBC when an EISA
master is accessing a host bus slave or the ISP. It is an output from the EBC during EISA master
cycles to ISA slaves and is derived from CHRDY. It is an output for CPU cycles to ISA slaves
for which an EISA cycle has been initiated.
Locked cycle (LOCK#) is an output signal which indicates to EISA slaves that the host CPU is
executing a locked cycle. It is asserted by the EBC when the HLOCK# signal is asserted.
8.3.4.2

EBC and ISA Bus Interface Signals

Bus address latch enable (BALE) is an output from the EBC which indicates that a valid address
is present on the latched address (LA) bus.
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