Introduction; Processor And Cache Feature Overview; The Burst Cycle - Intel Embedded Intel486 Hardware Reference Manual

5.1

INTRODUCTION

The Intel486™ processor contains several improvements over its predecessor, the highly suc-
cessful Intel386™ processor. One of the most important of these is the processor's data access
rate. The Intel486 processor can access instructions and data from its on-chip cache in the same
clock cycle. To support the processor's redesigned internal data path, the external bus has also
been optimized and can access external memory at twice the rate of the Intel386 CPU. The inter-
nal cache requires rapid access to entire cache lines. Invalidation cycles must be supported to
maintain consistency with external memory. All of these functions must be supported by the ex-
ternal memory system. Without them, the full performance potential of the CPU cannot be at-
tained.
The requirements of multi-tasking and multiprocessor operating systems also place increased de-
mand on the external memory system. OS support functions such as paging and context switching
can degrade reference locality. Without efficient access to external memory, the performance of
these functions is degraded.
Second-level (also known as L2) caching is a technique used to improve the memory interface.
Some applications, such as multi-user office computers, require this feature to meet performance
goals. Single-user systems, on the other hand, may not warrant the extra cost. Due to the variety
of applications incorporating the Intel486 processor, memory system architecture is very diverse.
5.2

PROCESSOR AND CACHE FEATURE OVERVIEW

The improvements made to the processor bus interface impact the memory subsystem design. It
is important to understand the impact of these features before attempting to define a memory sub-
system. This section reviews the bus features that affect the memory interface.
The Ultra-Low Power Intel486 GX processor supports only a 16-bit external
data bus. The other Intel486 processors discussed in this manual feature
dynamic bus sizing to accommodate 32-, 16-, and 8-bit devices.
5.2.1

The Burst Cycle

The Intel486 processor's burst bus cycle feature has more impact on the memory logic than any
other feature. A large portion of the control logic is dedicated to supporting this feature. The L2
cache control is also primarily dedicated to supporting burst cycles.
To understand why the logic is designed this way, we must first understand the function of the
burst cycle. Burst cycles are generated by the CPU only when two events occur. First, the CPU
must request a cycle which is longer in bytes than the data bus can accommodate. Second, the
BRDY# signal must be activated to terminate the cycle. When these two events occur a burst cy-
MEMORY SUBSYSTEM DESIGN
NOTE
CHAPTER 5
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