Intel Embedded Intel486 Hardware Reference Manual page 75

Table 4-7. Transfer Bus Cycles for Bytes, Words and Dwords
Physical Byte Address in
Memory (Low Order Bits)
Transfer Cycles over 32-Bit
Bus
Transfer Cycles over 16-Bit
Bus
†
( = BS#16 asserted)
Transfer Cycles over 8-Bit
Bus
‡
( = BS8# Asserted)
KEY:
b = byte transfer h = high-order portion
w = 2-byte transfer l = low-order portion
3 = 3-byte transfer m = mid-order portion
d = 4-byte transfer
The function of unaligned transfers with dynamic bus sizing is not obvious. When the external
systems asserts BS16# or BS8#, forcing extra cycles, low-order bytes or words are transferred
first (opposite to the example above). When the Intel486 processor requests a 4-byte read and the
external system asserts BS16#, the lower two bytes are read first followed by the upper two bytes.
In the unaligned transfer described above, the processor requested three bytes on the first cycle.
When the external system asserts BS16# during this 3-byte transfer, the lower word is transferred
first followed by the upper byte. In the final cycle, the lower byte of the 4-byte operand is trans-
ferred, as shown in the 32-bit example above.
Byte-Length of Logical Operand
1 2
xx 00 01
b w w
†
b w lb
†
hb
‡ ‡
b lb lb
‡ ‡
hb hb
4-Byte Operand
10 11 00
w hb d
lb
†
w hb lw
†
lb hw
‡ ‡
lb hb lb
‡ ‡
hb lb mlb
‡
mhb
‡
hb mhb
lb
↑ byte with
lowest address
BUS OPERATION
4
01 10 11
hb hw h3
l3 lw lb
†
hb hw mw
† †
lb lw hb
†
mw lb
‡ ‡
hb mhb mlb
‡ ‡ ‡
lb hb mhb
‡ ‡ ‡
mlb lb hb
‡ ‡
mlb lb
mlb mhb hb
↑byte with
highest address
4-11