Pci Bus Cycles Support - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
External Address, EADS#, when asserted, indicates that an external address has been driven onto
the CPU address lines. This address is used to perform an internal cache snoop cycle. This signal
is deasserted after a hard reset.
Cache Enable, KEN#, when asserted, indicates whether the current cycle is cacheable in the CPU
L1 cache. This signal is deasserted after a hard reset.
Hit Modified, HITM#, when asserted, indicates that a hit to a modified data cache has occurred
during the snoop cycle. A pull-up is used to keep HITM# deasserted when not used.
The system controller has a standard master/slave PCI bus interface. As a PCI device, the system
controller can be either a master initiating a PCI bus operation or a target responding to a PCI bus
operation. The system controller is a PCI bus master for Host-to-PCI accesses and a target for
PCI-to-main memory accesses (or accesses that are forwarded to the ISA bus). The Host can read
or write configuration spaces, PCI memory space, and PCI I/O space.
8.4.3.4

PCI Bus Cycles Support

When the host initiates a bus cycle to a PCI device, the system controller becomes a PCI bus mas-
ter and translates the CPU cycle into the appropriate PCI bus cycle. Post buffers permit the CPU
to complete Host-to-PCI writes in zero wait-states.
When a PCI bus master initiates a main memory access, the system controller becomes the target
of the PCI bus cycle and responds to the read/write access. As a PCI master, the system controller
generates address parity for read and write cycles, and data parity for write cycles. As a target,
the system controller generates data parity for read cycles. During PCI-to-main memory accesses,
the system controller automatically performs cache snoop operations on the Host bus, if needed,
to maintain data consistency.
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