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must handle all of the writes. A later section examines bus utilization and on-chip cache hit rates
in more detail.
Table 9-1. Typical Instruction Mix and Execution Times for
Instruction
Move R,M
Move M,R
Push R
Move R,R
Move R,I
JCC taken
JCC fail
ALU2 R,R
POP R
JMP M
ALU2 R,M
ALU2 M,I
Call
Shift R
ALU2 R,I
RET
String
ALU1 R
LDS
ALU2 M,R
ALU1 M
Push M
NOP
Others
Average clocks per instruction
NOTE: All percentages are approximate.
the Intel486™ Processor
Percentage
Utilization
16.2%
6.9%
6.1%
5.7%
5.5%
4.6%
4.5%
4.3%
4.0%
2.9%
2.9%
2.9%
2.8%
2.8%
2.8%
2.7%
2.6%
1.2%
1.4%
1.3%
1.2%
1.1%
1.1%
11.7%
PERFORMANCE CONSIDERATIONS
Intel486™
Processor
Accumulated
Clocks
1.16
1
1
1
1
3.4
1
1
1.16
3.4
2.16
3.16
3.4
2
1
5.56
3.16
1
12
3.16
3.16
2.16
1
2.25
Intel486™
Clocks
0.188
0.069
0.061
0.057
0.055
0.156
0.045
0.043
0.046
0.099
0.063
0.092
0.095
0.056
0.028
0.028
0.150
0.082
0.020
0.168
0.041
0.024
0.011
0.263
1.95
9-3
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