Intel Embedded Intel486 Hardware Reference Manual page 251

board controller. Edge/level interrupts and interrupt steering are supported for PCI plug-and-play
compatibility. The ISA bridge integrates the ISA address and data path, reducing TTL and system
cost. In addition, the integration of system clock generation logic eliminates the need for external
host and PCI clock drivers.
A17–A2
CMDV#
SIDLE#
LREQ#
LGNT#
SMI#
STPCLK#
EXTSMI#
CLK2IN
CLK2OUT
HCKLOUT2–HCKLOUT1
HCLKIN
SYSCLK
PCICLK2–PCICLK1
CPURST
RSTDRV
PCIRST
SRESET
PWROK#
XBUSTR#
XBUSOE#
BIOSCS#
KBCCS#
RTCCS#
RTCALE
FERR#
IGNNE#
OSC
SPKR
PCI
ISA Bridge
Link
Interface
SMM
Interface
Clock
Interface
Reset
Interface
X-Bus
Interface
Timers/
Counters
1x82C54
Figure 8-7. ISA Bridge Block Diagram
SYSTEM BUS DESIGN
IOCS16#
MEMCS16#
ZEROWS#
MEMR#
MEMW#
SMEMR#
SMEMW#
IOCHRDY
ISA Bus
BALE
Interface
IOR#
IOW#
LA23–LA17
SA19–SA0
SD15–SD0
SBHE#
AEN
IOCHK#
NMI
SERR#
Interface
NMI
DREQ7–DREQ5
DREQ3–DREQ0
DACK7–DACK5
DMA
DACK3–DACK0
2x82C37
TC
REFRESH#
IRQ8#
IRQ(15,14,11:9,7:3,1)
Interrupt
IRQ12/M
2x82C59
INTR
PIRQ0#
PIRQ1#
Test
TESTIN#
8-23