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64-Bit Interunit Transfer Bus
Base/
Barrel
Segmentation
Index
Shifter
Unit
Bus
Descriptor
Register
32
Registers
File
Limit and
ALU
Attribute PLA
Micro-
Instruction
Control &
Protection
Test Unit
Decoded
Instruction
Control
Path
ROM
Figure 3-2. Intel486™ SX Processor Block Diagram
32-Bit Data Bus
32-Bit Data Bus
Linear Address
32
PCD
PWT
2
Cache Unit
Paging
Unit
20
Physical
8 Kbyte
Address
Cache
Translation
Lookaside
Buffer
Displacement Bus
32
Prefetcher
32-Byte Code
Queue
Code
Stream
2x16 Bytes
Instruction
24
Decode
INTERNAL ARCHITECTURE
Bus Interface
A31-A2
BE3#- BE0#
Address
32
Drivers
Write Buffers
32
4 x 32
D31-D0
Data Bus
32
Transceivers
ADS# W/R# D/C# M/IO#
Bus Control
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
FERR# IGNNE#
STPCLK#
Request
Sequencer
BRDY# BLAST#
Burst Bus
Control
BS16# BS8#
Bus Size
Control
KEN# FLUSH#
Cache
AHOLD EADS#
Control
Parity
DP3-DP0 PCHK#
Generation
and Control
TCK TMS
Boundary
TDI TD0
Scan
Control
A5443-01
3-3
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