Intel Embedded Intel486 Hardware Reference Manual page 330

Embedded intel486 processor
Table of Contents

Advertisement

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
C
Cache
see also Level-1 cache or Second-level cache
6-9
4-way set associative,
6-10
block size,
6-14
broadcasting,
configuration options,
4-52
6-13
consistency,
,
6-1
defined,
6-6
direct mapped,
9-6
effect on bus cycles,
external
see Second-level cache
6-5
fully associative,
hardware transparency,
6-3
9-6
hit rates (L1),
,
3-12
invalidating lines,
memory hierarchy and,
memory mapped I/O devices,
multi-processor systems,
non-cacheable regions,
2-6
3-4
7-28
on-chip,
,
,
3-11
organization on-chip,
6-2
performance issues,
3-12
6-11
replacement,
,
6-9
sector buffering,
6-8
set associative,
single vs. multiple processor systems,
3-10
structure,
two-way set associative,
3-12
updating,
updating main memory,
3-12
6-13
write-back,
,
3-12
6-12
write-through,
,
Cache enable (KEN#) signal,
6-16
Cache transparency,
3-10
Cache unit,
4-21
Cacheable cycles,
,
1-1
Chapter summaries,
Chip capacitors, decoupling,
10-1
CHMOS IV process,
1-4
Clear, defined,
Clock (CLK) signal
10-30
skew,
Index-2
3-13
7-28
,
6-14
6-19
7-27
6-16
3-12
9-4
,
9-4
,
6-5
9-4
to
,
6-16
6-8
6-11
5-2
5-4
to
5-2
5-4
to
10-8
10-30
Clock considerations,
10-32
Clock routing,
10-31
Clock timings,
Control registers
10-42
debug,
3-14
Control unit,
2-12
Controllers, embedded,
10-25
Cross-talk,
1-5
Customer service,
D
10-24
Daisy chaining,
5-1
Data access rate,
7-32
Data buffers,
Data bus
2-1
dynamic bus sizing,
7-26
Data transceivers,
3-8
4-1
Data transfer,
,
3-14
Datapath unit,
1-4
Deassert, defined,
10-42
Debug control register,
10-39
Debug registers,
to
10-37
10-43
Debugging,
,
features of the Intel486 processor,
10-6
Decoupling capacitors,
10-36
Derating curve,
6-6
Direct mapped cache,
DMA
6-16
cache and,
in multiple processor system,
in single processor system,
DMA controller
8-33
82420EX PCIset,
8-16
in EISA designs,
1-6
Documents, related,
1-4
DOS address, defined,
DRAM
5-6
clock latencies,
9-14
design,
9-14
interleaving,
Dynamic data bus sizing,
10-32
to
4-3
,
10-41
10-39
4-14
4-15
to
4-12
4-13
to
2-1
4-3
7-3
,
,

Advertisement

Table of Contents
loading

Table of Contents