Byte Enables During A Cache Line Fill - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
paging is disabled, or to cache the page directory entry, control register 3 (CR3) must have
PCD=0.
4. The cache disable (CD) bit in control register 0 (CR0) must be clear.
External hardware can determine when the Intel486 processor has transformed a read or prefetch
into a cache fill by examining the KEN#, M/IO#, D/C#, W/R#, LOCK#, and PCD pins. These
pins convey to the system the outcome of conditions 1–3 in the above list. In addition, the
Intel486 processor drives PCD high whenever the CD bit in CR0 is set, so that external hardware
can evaluate condition 4.
Cacheable cycles can be burst or non-burst.
4.3.3.1

Byte Enables during a Cache Line Fill

For the first cycle in the line fill, the state of the byte enables should be ignored. In a non-cache-
able memory read, the byte enables indicate the bytes actually required by the memory or code
fetch.
The Intel486 processor expects to receive valid data on its entire bus (32 bits) in the first cycle of
a cache line fill. Data should be returned with the assumption that all the byte enable pins are as-
serted. However if BS8# is asserted, only one byte should be returned on data lines D7–D0. Sim-
ilarly if BS16# is asserted, two bytes should be returned on D15–D0.
The Intel486 processor generates the addresses and byte enables for all subsequent cycles in the
line fill. The order in which data is read during a line fill depends on the address of the first item
read. Byte ordering is discussed in
4-22
Section 4.3.4, "Burst Mode Details."