Intel Embedded Intel486 Hardware Reference Manual page 45

The Intel486™ SX processor has a 32-bit architecture with on-chip memory management and
level-1 cache.
The IntelDX2™ and IntelDX4™ processors also have a 32-bit architecture with on-chip memory
management and cache, but add clock multiplier and floating-point units. The Intel486 SX and
Intel486 DX processors support dynamic bus sizing for the external data bus; that is, the bus size
can be specified as 8-, 16-, or 32-bits wide.
Internally, the ultra-low power processors are similar to the Intel486 SX processor, but add a
clock control unit. Although the Ultra-Low Power Intel486 SX supports dynamic bus sizing, the
Ultra-Low Power Intel486 GX supports only a 16-bit external data bus. The Ultra-Low Power
Intel486 GX also has advanced power management features.
Table 3-1 lists the functional units of the embedded Intel486 processors.
Table 3-1. Intel486™ Processor Family Functional Units
Functional Unit
Bus Interface
Cache (L1)
Instruction Prefetch
Instruction Decode
Control
Integer and Datapath
Segmentation
Paging
Floating-Point
Clock Multiplier
Clock Control
Figure 3-1 is a block diagram of the embedded IntelDX2 and IntelDX4 processors. Note that the
cache unit is 8-Kbytes for the IntelDX2 processor and 16 Kbytes for the IntelDX4 processor.
Figure 3-2 is a block diagram of the embedded Intel486 SX processor and
diagram of the Ultra-Low Power Intel486 SX and the Ultra-Low Power Intel486 GX processors.
INTERNAL ARCHITECTURE
IntelDX2™ and
IntelDX4™ Processors
CHAPTER 3
Intel486™ SX
Processor
Intel486 GX Processors
Figure 3-3
Ultra-Low Power
Intel486 SX and
Ultra-Low Power
is a block
3-1