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V
= V
· {75/(75+30)} = 2.64286 V
a
S
V
= 2.64286 x 0.14286 = 0.37755 V
r1
V
= 0.37755 x –0.42875 = –0.16181 V
r2
V
= –0.16181 x 0.14286 = –0.02312 V
r3
V
= –0.02312 x –0.42857 = 0.00991 V
r4
V
= 0.00991 x 0.14286 = 0.00142 V
r5
V
= 0.00142 x –0.42857 = –0.00061 V
r6
V
= –0.00061 x 0.14286 = –0.00009 V
r7
Figure 10-12
shows the corresponding lattice diagram.
A
V(A,t) t = 0
2.857 V 2t
pd
2.845 V 4t
pd
2.846 V 6t
pd
Impedance discontinuity problems are managed by imposing limits and control during the rout-
ing phase of the design. Design rules must be observed to control trace geometry, including spec-
ification of the trace width and spacing for each layer. This is very important because it ensures
the traces are smooth and constant without sharp turns.
PHYSICAL DESIGN AND SYSTEM DEBUGGING
Figure 10-12. Lattice Diagram Example
B
V(B,t)
t
3.02 V
pd
3t
2.835 V
pd
5t
2.847 V
pd
7t
2.846 V
pd
10-17
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