R
3.2.2
Design Considerations
• Standard vias should be 14 mil hole with a 26 mil pad.
Figure 9. Example Stack-Up for 6-Layer ATX Form Factor
®
®
Intel
Pentium
4 Processor / Intel
Top - Signal
(plated 1/2oz C u)
L2 - Power
(unplated 1oz Cu)
L3 - Signal
(unplated 1oz Cu)
C ore
L4 - Signal
(unplated 1oz Cu)
L5 - G round
(unplated 1oz C u)
Bot - Signal
(plated 1/2oz C u)
®
850 Chipset Family Platform Design Guide
Platform Placement and Stack-Up Overview
2.1 m ils
A
C
1.2 m ils
D
B
1.2 m ils
E
6.5 m ils
F
6.5 m ils
E
1.2 m ils
B
D
1.2 m ils
C
2.1 m ils
A
Total
1 oz L2 / L5
Thickness
T olerance
(m ils)
(±m ils)
2.1
0.4
4
0.3
1.2
0.2
4.3
0.5
1.2
0.2
6.5
0.5
23
0.5
6.5
0.5
1.2
0.2
4.3
0.5
1.2
0.2
4
0.3
2.1
0.4
61.6
4.7
Stack_ATX_850-P4
37