Intel Embedded Intel486 Hardware Reference Manual page 106

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
The latency between a STPCLK# request and the Stop Grant bus cycle is dependent on the cur-
rent instruction, the amount of data in the processor write buffers, and the system memory per-
formance.
Cycle Name
†
Write-Back
First Flush Ack Cycle
†
Flush
Second Flush Ack Cycle
Shutdown
HALT
Stop Grant Ack Cycle
†
These cycles are specific to the Write-Back Enhanced IntelDX4™ processor. The FLUSH# cycle is
applicable to all Intel486™ processors. See appropriate sections for details.
CLK
STPCLK#
ADDR Data
BRDY# or RDY#
4-42
Table 4-9. Special Bus Cycle Encoding
M/IO#
0
†
0
0
†
0
0
0
0
T T
su hd
Figure 4-32. Stop Grant Bus Cycle
D/C# W/R#
0 1
0 1
0 1
0 1
0 1
0 1
0 1
BE3#–BE0# A4-A2
0111 000
0111 001
1101 000
1101 001
1110 000
1011 000
1011 100
Stop Grant Cycle
A4401-01