Intel Embedded Intel486 Hardware Reference Manual page 157

31
Cache/DRAM
Select
Cache-64 Kbyte
Index
TAG
FFFC
01
FFF8 FF
0008 00
0004 01
00
0000
If the processor requests data at FFFFF8, the first step is to send the least significant 14 bits of
FFF8 to the cache tag RAM. If the tag field stored at FFF8 is FF (as shown in the diagram), then
a hit has occurred and the data word ''B'' is sent to the CPU. If the requested word has 020004,
then the tags would not match. In this case the tag RAM would be updated with the value 02 cor-
responding to the index 0004, and the data ''D'' would be replaced by the word at location
020004.
If the processor accesses locations that have the same index bits, then the cache would have to be
updated constantly. This type of program behavior is infrequent, however, so a direct mapped
32-Bit Processor Address
24 23
TAG
Data
A
B
C
D
E
32 Bits
Figure 6-2. Direct Mapped Cache Organization
16 15
Index
64 Kbyte Cache 16 Bits
16 Mbyte DRAM 24 Bits
Main Memory - 16 MB
Data
Y
B
A
D
C
E
CACHE SUBSYSTEM
0
TAG
Index
FFFC
FFF8
0008
0004
0000
FFFC
FFF8
0008
0004
0000
FFFC
FFF8
0008
0004
0000
6-7