Floating-Point Performance - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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Figure 9-7. Performance in Systems with and without Posted Writes
9.9

FLOATING-POINT PERFORMANCE

9.9.1 Floating-Point Execution Sequences
The floating-point unit on the Intel486 processor contains the logic to execute the floating-point
instruction set that is 100% binary compatible to Intel math coprocessors. The floating-point unit
operates in parallel with the arithmetic and logic unit, and provides arithmetic functions and tran-
scendental functions. The enhanced floating-point unit provides three to four times the perfor-
mance of a non-integrated Intel math coprocessor.
An overlap of floating-point instruction execution and non-floating point instruction execution
increases the overall throughput.
The floating-point unit can take advantage of pipelined instruction execution. Within the Intel486
processor, the floating-point instructions share the microcode ROM with integer instructions.
However, floating-point operations do not utilize the microcode ROM after the operation has
been prepared for execution. For example, only the first three clocks of the floating-point add,
multiply and divide instructions use the microcode ROM. After the third clock, the floating-point
unit completes the operations independently, and the microcode ROM can be utilized by non-
floating-point instructions.
Another feature that enhances performance is an efficient on-chip interface. The Intel386 DX
CPU and the Intel math coprocessor communicate asynchronously, whereas the Intel486 proces-
sor communicates with its on-chip floating-point unit synchronously, allowing higher perfor-
mance.
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Intel486™ CPU Performance vs. Optimized Write
Application C with
Posted Writes
Application C without
Posted Writes
Application D with
Posted Writes
Application D without
Posted Writes