On-Chip Cache; Floating-Point Unit - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
2.2.3

On-chip Cache

A software-transparent 8-Kbyte cache (16-Kbyte on the IntelDX4 processor) stores recently ac-
cessed information on the processor. Both instructions and data can be cached. If the processor
needs to read data that is available in the cache, the cache responds, thereby avoiding a time-con-
suming external memory cycle. This allows the processor to complete transfers faster and reduces
traffic on the processor bus.
The internal cache on all members of the Intel486 processor family uses a write-through protocol.
The IntelDX4 processor can also be configured to implement a write-back protocol. With a write-
through protocol, all writes to the cache are immediately written to the external memory that the
cache represents. With a write-back protocol, writes to the cache are stored for future memory
updating. To reduce the impact of writes on performance, the processor can buffer its write cy-
cles; an operation that writes data to memory can finish before the write cycle is actually per-
formed on the processor bus.
The processor performs a cache line fill to place new information into the on-chip cache. This
operation reads four doublewords into a cache line, the smallest unit of storage that can be allo-
cated in the cache. Most read cycles on the processor bus result from cache misses, which cause
cache line fills.
The Intel486 processor provides mechanisms to maintain cache consistency between memory
and cached data in multiple bus master environments. These mechanisms protect the Intel486
processor from reading invalid data from its own internal cache or from external caches. For ex-
ample, when the Intel486 processor attempts to read an operand from memory that is also held in
the cache of another bus master, the other bus master is forced to write its cached data back to
memory before the Intel486 processor can complete its read from memory. This is done because
the cached version of the data may have been updated, and so may now be different from the ver-
sion stored in memory.
Most memory systems optimize the speed of access on a read cycle. This is because the large ma-
jority of all memory accesses in a typical system are read accesses. The Intel486 processor's in-
ternal cache changes this ratio. Most read requests result in cache hits, so most memory accesses
on the processor bus are write cycles. Memory optimization should be done with this in mind.
2.2.4

Floating-Point Unit

The internal floating-point unit performs floating-point operations on the 32-, 64- and 80-bit
arithmetic formats as specified in IEEE Standard 754. Like the integer processing unit, the float-
ing-point unit architecture is binary-compatible with the 8087 and 80287 coprocessors. The ar-
chitecture is 100% compatible with the Intel387 DX and Intel387 SX coprocessors.
Floating-point instructions execute fastest when they are entirely internal to the processor. This
occurs when all operands are in the internal registers or cache. When data needs to be read from
or written to external locations, burst transfers minimize the time required and a bus locking
mechanism ensures that the bus is not relinquished to other bus masters during the transfer. Bus
signals are provided to monitor errors in floating-point operations and to control the processor's
response to such errors.
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