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SYSTEM BUS DESIGN
for each of the bytes. It also has an EISA address mode in which the addresses are interfaced with
internal latched transceivers. Polarity on the address lines is compatible with the EISA specifica-
tion, so that, for example, the most significant address byte is inverted.
8.3.3
EBC Host Bus Interface
The EBC resides between a fast host bus and the EISA bus and monitors cycles that are initiated
on either bus. When the host initiates a bus master cycle and no response is received from the host
slaves, the EBC forwards the cycle to the EISA bus. When an EISA bus master initiates a cycle,
then it is always forwarded to the host bus. The EBC provides controls to the EBB device for the
address and the data buffers between the two buses. The EBC also inserts delays between back-
to-back I/O cycles between the host and the EISA bus.
8.3.3.1
Clock, Control and Status Interface
The host CPU clock (HCLKCPU) runs at the same frequency as the CPU clock. The EBC divides
the HCLKCPU appropriately to generate the EISA BCLK signal.
Host address status (HADS1–HADS0) input signals indicate to the EBC that the addresses, byte
enables, and cycle type information is valid on the host. These two signals are received by the
EBC when there is a master on the host bus and are used to track the host bus cycles. If a host
slave does not respond, and if an EISA/ISA slave or ISP is being addressed, then one or more
cycles are generated on the EISA bus.
Host byte enables (HBE3#–HBE0#) are bidirectional signals that indicate valid bytes during an
operation. They are inputs during host bus master cycles and are outputs during EISA bus master
cycles as well as when the ISP is performing DMA or refresh cycles.
Host Byte High Enable (HBHE#) is a bidirectional signal. When asserted, it indicates that the up-
per byte of the 16-bit host bus is involved in the transfer. It is an input during host bus master
cycles when an EISA/ISA slave is being accessed and an output during EISA master cycles or
when the ISP is performing DMA or refresh cycles.
Host address bits 1,0 (HA1, HA0) are bidirectional signals that are used in the Intel386™ SX mi-
croprocessor systems.
Host next address (HNA#) is an output to the host CPU when it accesses an EISA/ISA slave.
HNA# is asserted to indicate that the CPU can put a new address on the host bus.
Host data or control (HD/C#) is a bidirectional signal that differentiates between data and control
cycles. It is an input to the EBC during host bus master cycles and is used to decode shutdown
and interrupt acknowledge cycles. It is an output from the EBC during EISA/ISA master cycles
and when the ISP performs DMA or refresh cycles. The signal is asserted to a high level when it
is an output.
Host write or read (HW/R#) is a bidirectional signal that distinguishes between read and write
cycles. It is an input to the EBC on host bus master is accessing an EISA/ISA slave, or when the
ISP is performing DMA or refresh cycles. It is an output from the EBC on EISA/ISA master cy-
cles.
Host memory or I/O (HMI/O#) is a bidirectional signal that differentiates between memory and
I/O cycles. It is an input to the EBC when the host bus master cycles and is an output from the
8-9
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