Intel Embedded Intel486 Hardware Reference Manual page 270

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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Figure 9-1. Cache Hit Rate for Various Programs
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B
C
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E
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9.3.3 Bus Cycle Mix with and without On-Chip Cache
Microprocessors that lack an on-chip cache must devote a significant portion of execution time
to external bus accesses. Code prefetches and data reads must come from the external memory
system; subsequently a high percentage of bus accesses are reads. Traditional memory systems
are optimized for reads because of this mix of bus cycles.
With the Intel486 processor's on-chip cache, however, the high hit rate reduces the number of ex-
ternal reads. As the on-chip cache implements a write-through policy, the number of writes to the
bus is not reduced. As a result, external bus read cycles are now a minor portion of the overall
9-6
On-Chip Cache Hit Rates
B C
Program
Table 9-2. Programs Used
Name
FRAME
PHONGS4
Sunview
INVFRAME
TPASCAL
TROFF
E
D
Description
Desktop publishing package
Small benchmark program
Window manager
Desktop publishing package
Pascal compiler
Text Formatter
Prefetches
Reads