Locked Cycles - Intel Embedded Intel486 Hardware Reference Manual

BUS OPERATION
4.4.4

Locked Cycles

In both Standard and Enhanced Bus modes, the Write-Back Enhanced IntelDX4 processor archi-
tecture supports atomic memory access. A programmer can modify the contents of a memory
variable and be assured that the variable is not accessed by another bus master between the read
of the variable and the update of that variable. This function is provided for instructions that con-
tain a LOCK prefix, and also for instructions that implicitly perform locked read modify write
cycles. In hardware, the LOCK function is implemented through the LOCK# pin, which indicates
to the system that the processor is performing this sequence of cycles, and that the processor
should be allowed atomic access for the location accessed during the first locked cycle.
A locked operation is a combination of one or more read cycles followed by one or more write
cycles with the LOCK# pin asserted. Before a locked read cycle is run, the processor first deter-
mines if the corresponding line is in the cache. If the line is present in the cache, and is in an E or
S state, it is invalidated. If the line is in the M state, the processor does a write-back and then in-
validates the line. A locked cycle to an M, S, or E state line is always forced out to the bus. If the
operand is misaligned across cache lines, the processor could potentially run two write back cy-
cles before starting the first locked read. In this case the sequence of bus cycles is: write back,
write back, locked read, locked read, locked write and the final locked write. Note that although
a total of six cycles are generated, the LOCK# pin is asserted only during the last four cycles, as
shown in Figure 4-46.
LOCK# is not deasserted if AHOLD is asserted in the middle of a locked cycle. LOCK# remains
asserted even if there is a snoop write-back during a locked cycle. LOCK# is floated if BOFF# is
asserted in the middle of a locked cycle. However, it is driven LOW again when the cycle restarts
after BOFF#. Locked read cycles are never transformed into line fills, even if KEN# is asserted.
If there are back-to-back locked cycles, the Write-Back Enhanced IntelDX4 processor does not
insert a dead clock between these two cycles. HOLD is recognized if there are two back-to-back
locked cycles, and LOCK# floats when HLDA is asserted.
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