Intel Embedded Intel486 Hardware Reference Manual page 12

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Figure
4-32 Stop Grant Bus Cycle .................................................................................................4-42
4-33 Restarted Read Cycle ................................................................................................4-43
4-34 Restarted Write Cycle.................................................................................................4-44
4-35 Bus State Diagram .....................................................................................................4-45
4-36 DOS-Compatible Numerics Error Circuit ....................................................................4-49
4-37 Basic Burst Read Cycle..............................................................................................4-51
4-38 Snoop Cycle Invalidating a Modified Line...................................................................4-55
4-39 Snoop Cycle Overlaying a Line-Fill Cycle ..................................................................4-57
4-40 Snoop Cycle Overlaying a Non-Burst Cycle...............................................................4-58
4-41 Snoop to the Line that is Being Replaced ..................................................................4-60
4-42 Snoop under BOFF# during a Cache Line-Fill Cycle .................................................4-62
4-43 Snoop under BOFF# to the Line that is Being Replaced............................................4-63
4-44 Snoop under HOLD during Line Fill............................................................................4-65
4-45 Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch............4-66
4-46 Locked Cycles (Back-to-Back) ...................................................................................4-68
4-47 Snoop Cycle Overlaying a Locked Cycle ...................................................................4-69
4-48 Flush Cycle.................................................................................................................4-70
4-49 Snoop under AHOLD Overlaying Pseudo-Locked Cycle ...........................................4-71
4-50 Snoop under HOLD Overlaying Pseudo-Locked Cycle..............................................4-72
4-51 Snoop under BOFF# Overlaying a Pseudo-Locked Cycle .........................................4-73
5-1 Typical Burst Cycle.......................................................................................................5-3
5-2 Burst Cycle: KEN# Normally Active..............................................................................5-4
5-3 Intel386™ Processor Bus Cycle Mix/Intel486™ Processor Bus Cycle Mix..................5-5
6-1 A Fully Associative Cache Organization.......................................................................6-5
6-2 Direct Mapped Cache Organization .............................................................................6-7
6-3 Two-Way Set Associative Cache Organization ............................................................6-8
6-4 Sector Buffer Cache Organization................................................................................6-9
6-5 The Cache Data Organization for the Intel486™ Processor's On-Chip Cache..........6-10
6-6 Stale Data Problem in the Cache/Main Memory ........................................................6-12
6-7 Bus Watching/Snooping for Shared Memory Systems...............................................6-14
6-8 Hardware Transparency .............................................................................................6-14
6-9 Non-Cacheable Share Memory ..................................................................................6-15
6-10 Intel486™ Processor System Arbitration....................................................................6-17
6-11 A Typical Intel486™ Processor System .....................................................................6-18
6-12 Intel486™ Processor System Memory Hierarchy.......................................................6-19
7-1 Mapping Scheme .........................................................................................................7-2
7-2 Intel486™ Processor Interface to I/O Devices .............................................................7-6
7-3 Logic to Generate A1, BHE# and BLE# for 16-Bit Buses.............................................7-7
7-4 Intel486™ Processor Interface to 8-Bit Device.............................................................7-8
7-5 Bus Swapping 16-Bit Interface ...................................................................................7-11
7-6 Bus Swapping and Low Address Bit Generating Control Logic..................................7-14
7-7 32-Bit I/O Interface .....................................................................................................7-15
7-8 System Block Diagram ...............................................................................................7-17
7-9 Basic I/O Interface Block Diagram..............................................................................7-19
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