General Design Considerations; Nominal Board Stackup; Sample Board Stackup - Intel Pentium III Design Manual

General Design Considerations

This section documents motherboard layout and routing guidelines for Intel
512KB L2 Cache platforms. This section does not discuss the functional aspects of any bus, or the layout
guidelines for an add-in device.
If the guidelines listed in this document are not followed, it is very important that thorough signal integrity
and timing simulations are completed for each design. Even when the guidelines are followed, critical
signals are recommended to be simulated to ensure proper signal integrity and flight time. Any deviation
from the guidelines should be simulated.
The trace impedance typically noted (i.e., 60Ω +/- 15%) is the "nominal" trace impedance for a 5-mil wide
trace. That is, the impedance of the trace when not subjected to the fields created by changing current in
neighboring traces. When calculating flight times, it is important to consider the minimum and maximum
impedance of a trace based on the switching of neighboring traces. Using wider spaces between the
traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces, the
signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the effects
of trace-to-trace coupling, the routing guidelines documented in this section should be followed.
2.1

Nominal Board Stackup

An example of a 6-layer stack-up is shown in
be 60Ω +/- 15%. A lower trace impedance reduces signal edge rates, overshoot, and undershoot, and
has less crosstalk than a higher trace impedance. A higher trace impedance increases edge rates and
may slightly decrease signal flight times. Please note that thicker core may help reduce board warpage
issues.
Figure 2-1. Sample Board Stackup
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Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
Figure 2-1. The impedance of all the signal layers should
Signal Layer
Gnd Plane (1 oz. cu.)
Signal Layer
Signal Layer
Pwr Plane (1 oz. cu.)
Signal Layer
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Pentium III Processor with
2
2-1