4.3.11 Special Bus Cycles; Halt Indication Cycle; Shutdown Indication Cycle; Stop Grant Indication Cycle - Intel Embedded Intel486 Hardware Reference Manual

4.3.11 Special Bus Cycles

The Intel486 processor provides special bus cycles to indicate that certain instructions have been
executed, or certain conditions have occurred internally. The special bus cycles are identified by
the status of the pins shown in
During these cycles the address bus is driven low while the data bus is undefined.
Two of the special cycles indicate halt or shutdown. Another special cycle is generated when the
Intel486 processor executes an INVD (invalidate data cache) instruction and could be used to
flush an external cache. The Write Back cycle is generated when the Intel486 processor executes
the WBINVD (write-back invalidate data cache) instruction and could be used to synchronize an
external write-back cache.
The external hardware must acknowledge these special bus cycles by asserting RDY# or
BRDY#.
4.3.11.1

HALT Indication Cycle

The Intel486 processor halts as a result of executing a HALT instruction. A HALT indication cy-
cle is performed to signal that the processor has entered into the HALT state. The HALT indica-
tion cycle is identified by the bus definition signals in special bus cycle state and by a byte address
of 2. BE0# and BE2# are the only signals that distinguish HALT indication from shutdown indi-
cation, which drives an address of 0. During the HALT cycle, undefined data is driven on D31–
D0. The HALT indication cycle must be acknowledged by RDY# asserted.
A halted Intel486 processor resumes execution when INTR (if interrupts are enabled), NMI, or
RESET is asserted.
4.3.11.2

Shutdown Indication Cycle

The Intel486 processor shuts down as a result of a protection fault while attempting to process a
double fault. A shutdown indication cycle is performed to indicate that the processor has entered
a shutdown state. The shutdown indication cycle is identified by the bus definition signals in spe-
cial bus cycle state and a byte address of 0.
4.3.11.3

Stop Grant Indication Cycle

A special Stop Grant bus cycle is driven to the bus after the processor recognizes the STPCLK#
interrupt. The definition of this bus cycle is the same as the HALT cycle definition for the
Intel486 processor, with the exception that the Stop Grant bus cycle drives the value 0000 0010H
on the address pins. The system hardware must acknowledge this cycle by asserting RDY# or
BRDY#. The processor does not enter the Stop Grant state until either RDY# or BRDY# has been
asserted. (See Figure 4-32.)
The Stop Grant Bus Cycle is defined as follows:
M/IO# = 0, D/C# = 0, W/R# = 1, Address Bus = 0000 0010H (A4 = 1), BE3#–BE0# = 1011, Data
bus = undefined.
Table 4-9.
BUS OPERATION
4-41