Intel Embedded Intel486 Hardware Reference Manual page 120

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Snoop under AHOLD Overlaying a Line-Fill Cycle
The assertion of AHOLD during a line fill is allowed on the Write-Back Enhanced IntelDX4 pro-
cessor. In this case, when a snoop cycle is overlaid by an on-going line-fill cycle, the chipset must
generate the burst addresses internally for the line fill to complete, because the address bus has
the valid snoop address. The write-back mode is more complex compared to the write-through
mode because of the possibility of a line being written back. Figure 4-39 shows a snoop cycle
overlaying a line-fill cycle, when the snooped line is not the same as the line being filled.
In Figure 4-39, the snoop to an M-state line causes a snoop write-back cycle. The Write-Back En-
hanced IntelDX4 processor asserts HITM# two clocks after the EADS#, but delays the snoop
write-back cycle until the line fill is completed, because the line fill shown in Figure 4-39 is a
burst cycle. In this figure, AHOLD is asserted one clock after ADS#. In the clock after AHOLD
is asserted, the Write-Back Enhanced IntelDX4 processor floats the address bus (not the Byte En-
ables). Hence, the memory controller must determine burst addresses in this period. The chipset
must comprehend the special ordering required by all burst sequences of the Write-Back En-
hanced IntelDX4 processor. HITM# is guaranteed to remain asserted until the write-back cycle
completes.
If AHOLD continues to be asserted over the forced write-back cycle, the memory controller also
must supply the write-back addresses to the memory. The Write-Back Enhanced IntelDX4 pro-
cessor always runs the write-back with an address sequence of 0-4-8-C.
In general, if the snoop cycle overlays any burst cycle (not necessarily a line-fill cycle) the snoop
write-back is delayed because of the on-going burst cycle. First, the burst cycle goes to comple-
tion and only then does the snoop write-back cycle start.
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