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When a line is written back, KEN#, WB/WT#, BS8#, and BS16# are ignored, and PWT and PCD
are always low during write-back cycles.
1
CLK
AHOLD
EADS#
INV
HITM#
A31–A4
A3–A2
ADS#
BLAST#
CACHE#
BRDY#
W/R#
To Processor
*
Write-back from Processor
**
Figure 4-38. Snoop Cycle Invalidating a Modified Line
The next ADS# for a new cycle can occur immediately after the last RDY# or BRDY# of the
write-back cycle. The Write-Back Enhanced IntelDX4 processor does not guarantee a dead clock
between cycles unless the second cycle is a snoop-forced write-back cycle. This allows snoop-
forced write-backs to be backed off (BOFF#) when snooping under AHOLD.
HITM# is guaranteed to remain asserted until the RDY# or BRDY# signals corresponding to the
last doubleword of the write-back cycle is returned. HITM# is de-asserted from the clock edge in
which the last BRDY# or RDY# for the snoop write-back cycle is asserted. The write-back cycle
could be a burst or non-burst cycle. In either case, 16 bytes of data corresponding to the modified
line that has a snoop hit is written back.
2
3
4
5
*
6
7
8
9
* *
0
4
BUS OPERATION
10
11
12
13
8
C
242202-150
4-55
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