Burst Cycles - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
The external system can cause a multiple cycle transfer when it can only supply 8- or 16-bits per
cycle.
Only multiple cycle transfers caused by internal requests are considered in this section. Cache-
able cycles and 8- and 16-bit transfers are covered in Section 4.3.3, "Cacheable Cycles," and Sec-
tion 4.3.5, "8- and 16-Bit Cycles."
Internal Requests from IntelDX2 and IntelDX4 Processors
An internal request by an IntelDX2 or IntelDX4 processor for a 64-bit floating-point load must
take more than one internal cycle.
4.3.2.1

Burst Cycles

The Intel486 processor can accept burst cycles for any bus requests that require more than a single
data cycle. During burst cycles, a new data item is strobed into the Intel486 processor every clock
rather than every other clock as in non-burst cycles. The fastest burst cycle requires two clocks
for the first data item, with subsequent data items returned every clock.
The Intel486 processor is capable of bursting a maximum of 32 bits during a write. Burst writes
can only occur if BS8# or BS16# is asserted. For example, the Intel486 processor can burst write
four 8-bit operands or two 16-bit operands in a single burst cycle. But the Intel486 processor can-
not burst multiple 32-bit writes in a single burst cycle.
Burst cycles begin with the Intel486 processor driving out an address and asserting ADS# in the
same manner as non-burst cycles. The Intel486 processor indicates that it is willing to perform a
burst cycle by holding the burst last signal (BLAST#) deasserted in the second clock of the cycle.
The external system indicates its willingness to do a burst cycle by asserting the burst ready signal
(BRDY#).
The addresses of the data items in a burst cycle all fall within the same 16-byte aligned area (cor-
responding to an internal Intel486 processor cache line). A 16-byte aligned area begins at location
XXXXXXX0 and ends at location XXXXXXXF. During a burst cycle, only BE3#–BE0#, A2,
and A3 may change. A31–A4, M/IO#, D/C#, and W/R# remain stable throughout a burst. Given
the first address in a burst, external hardware can easily calculate the address of subsequent trans-
fers in advance. An external memory system can be designed to quickly fill the Intel486 processor
internal cache lines.
Burst cycles are not limited to cache line fills. Any multiple cycle read request by the Intel486
processor can be converted into a burst cycle. The Intel486 processor only bursts the number of
bytes needed to complete a transfer. For example, the IntelDX2 and Write-Back Enhanced
IntelDX4 processors burst eight bytes for a 64-bit floating-point non-cacheable read.
The external system converts a multiple cycle request into a burst cycle by asserting BRDY# rath-
er than RDY# (non-burst ready) in the first cycle of a transfer. For cycles that cannot be burst,
such as interrupt acknowledge and halt, BRDY# has the same effect as RDY#. BRDY# is ignored
if both BRDY# and RDY# are asserted in the same clock. Memory areas and peripheral devices
that cannot perform bursting must terminate cycles with RDY#.
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