Status And Control Interface - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
guarantee the CPU atomic LOCK sequence. Note that this PCI chip set supports a bus locking
mechanism (i.e., when a PCI master performs locked accesses, the arbitration is not changed until
the locked sequence is completed).
The system controller does not check parity or generate SERR# based on the PCI parity. The sys-
tem controller only generates SERR# (if enabled via the PCICOM register), when a main mem-
ory read results in a parity error. When main memory parity error is detected, the system
controller activates SERR#, if enabled, for a single PCICLK.
When a main memory parity error is detected and SERR# generation is enabled, the MMPERR
bit in the DS register is set to 1. When SERR# is activated, the SERRS bit in the DS register is
set to 1.
8.4.3.7

Status and Control Interface

Address/Data, AD31–AD0, are connected to the PCI multiplexed address/data bus. These signals
are also multiplexed with the IDE interface. These signals are driven high after a hard reset.
Bus Command/Byte Enable, C/BE3#–C/BE0#, are multiplexed on the same pins. These signals
are driven high after a hard reset.
FRAME# is an output when the system controller is a master on the PCI bus. FRAME# indicates
that a PCI cycle has started. This signal is 3-stated after a hard reset.
Target Ready, TRDY#, is an input when system controller is a master on the PCI bus. TRDY# is
an output when the system controller acts as a PCI slave. TRDY# indicates that the target device
is ready. This signal is 3-stated after a hard reset.
Initiator Ready, IRDY#, is an output when system controller is a PCI master. IRDY# is an input
when the system controller is a PCI slave. IRDY# indicates that the initiator of the cycle is ready.
This signal is 3-stated after a hard reset.
LOCK# indicates an exclusive bus operation and may require multiple transactions to complete.
The system controller supports a bus type of LOCK only. Thus, when a PCI master locks the PCI
bus, it owns the system for the duration of the locked transactions.
Stop, STOP#, indicates that the current bus target is requesting the master to stop the current
transaction. STOP# is used to disconnect, retry, and abort sequences on the PCI bus. This signal
is 3-stated after a hard reset.
Parity, PAR, is driven by the system controller, as a PCI master, during the address and data phas-
es for a write cycle and during the address phase for a read cycle. When the system controller is
a PCI slave, parity is driven by the system controller for the data phase of a PCI read cycle. Parity
is even across AD31–AD0 and C/BE3#–C/BE0#. PAR lags the corresponding address and data
phase by one PCICLK. This signal is asserted after a hard reset.
System Error, SERR#, when driven by the system controller, indicates that either a main memory
parity error occurred or the system controller, as a master, received a target abort.
Device Select, DEVSEL#, when asserted, indicates that a PCI slave device has decoded the bus
cycle address as the target of the current access. The system controller drives DEVSEL# based
on the main memory address range being accessed by a PCI master. As an input, DEVSEL# in-
dicates whether any device on the bus has been selected. This signal is 3-stated after a hard reset.
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