Locked Cycles; I/O Transfers - Intel Embedded Intel486 Hardware Reference Manual

writes as fast as one per clock. Once a write request is buffered, the internal unit that generated
the request is free to continue processing. If no higher-priority request is pending and the bus is
free, the transfer is propagated as an immediate write cycle to the processor bus. When all four
write buffers are full, any subsequent write transfer stalls inside the processor until a write buffer
becomes available.
The bus interface unit can re-order pending reads in front of buffered writes. This is done because
pending reads can prevent an internal unit from continuing, whereas buffered writes need not
have a detrimental effect on processing speed.
Writes are propagated to the processor bus in the first-in-first-out order in which they are received
from the internal unit. However, a subsequently generated read request (data or instruction) may
be re-ordered in front of buffered writes. As a protection against reading invalid data, this re-or-
dering of reads in front of buffered writes occurs only if all buffered writes are cache hits. Be-
cause an external read is generated only for a cache miss, and is re-ordered in front of buffered
writes only if all such buffered writes are cache hits, any read generated on the external bus with
this protection never reads a location that is about to be written by a buffered write. This re-or-
dering can only happen once for a given set of buffered writes, because the data returned by the
read cycle could otherwise replace data about to be written from the write buffers.
To ensure that no more than one such re-ordering is done for a given set of buffered writes, all
buffered writes are re-flagged as cache misses when a read request is re-ordered ahead of them.
Buffered writes thus marked are propagated to the processor bus before the next read request is
acted upon. Invalidation of data in the internal cache also causes all pending writes to be flagged
as cache misses. Disabling the cache unit disables the write buffers, which eliminates any possi-
bility of re-ordering bus cycles.
3.2.3

Locked Cycles

The processor can generate signals to lock a contiguous series of bus cycles. These cycles can
then be performed without interference from other bus masters, if external logic observes these
lock signals. One example of a locked operation is a semaphor read-modify-write update, where
a resource control register is updated. No other operations should be allowed on the bus until the
entire locked semaphor update is completed.
When a locked read cycle is generated, the internal cache is not read. All pending writes in the
buffer are completed first. Only then is the read part of the locked operation performed, the data
modified, the result placed in a write buffer, and a write cycle performed on the processor bus.
This sequence of operations ensures that all writes are performed in the order in which they were
generated.
3.2.4

I/O Transfers

Transfers to and from I/O locations have some restrictions to ensure data integrity:
•
Caching — I/O reads are never cached.
•
Read Re-ordering — I/O reads are never re-ordered ahead of buffered writes to memory.
This ensures that the processor has completed updating all memory locations before reading
status from a device.
INTERNAL ARCHITECTURE
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